Original title: Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
Yujie Zhang, Huiying Lan, Ehsan Aghapour, Zhiyuan Ning +4 · September 2026
Running smart computer programs on small computer chips is tricky. These chips have several different mini-processors. Usually, systems pass work along like an assembly line, called pipeliningSplitting a computation into stages so that different parts can be processed in sequence, improving overall throughput.. This approach finishes many tasks overall, but single tasks can take too long to complete. Running pieces of a program at the same time cuts waiting time, but picking one approach usually hurts the other. Researchers created Para-Pipe to solve this conflict. Para-Pipe combines both ideas into a multi-layered design. It runs parts of the work in an assembly line while also splitting individual tasks across different processors at each step. This method cuts down the time processors spend talking to each other, which saves power. Para-Pipe creates several balanced setups that balance speed and delay. On one test chip, its setups improved energy efficiency by 11.0% and 23.3% over older methods.
Imagine packing a suitcase for a trip where you need both business clothes and rain gear, but the suitcase has limited compartments. If you focus on fitting all items neatly, you might lose flexibility, or if you prioritize quick access, things might not fit well. In this paper, Para-Pipe is like a suitcase that dynamically adjusts its compartments based on what you need most, so you can carry both outfits without wasted space, by smartly organizing items as you pack.
For people using phones or gadgets with AI, this could mean quicker responses and longer battery life. By balancing how chips handle speed and multitasking, it tackles a key challenge in making everyday devices smarter without draining power.
The abstract does not state explicit limitations, but evaluations are performed only on specific Amlogic and Black Sesame SoCs, so generalizability to other platforms or real-world applications beyond these tests isn't confirmed.
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Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs — Yujie Zhang, Huiying Lan, Ehsan Aghapour et al.
Abstract licence: CC0
Explanation generated by Synthesis from the abstract — it is not the original paper. This is a preprint, so it hasn't necessarily been peer reviewed.